P598 - Conduction-Cooled FPGA-based USM Main PMC (Product Discontinued)

USM Universal Submodules make PMC modules more flexible than ever. The conduction-cooled main PMC P598 gets its specific function through the IP cores implemented inside the onboard FPGA. This function can be changed at any time through implementation of different IP cores. The corresponding line drivers are realized on the USM which is simply plugged on the P598.

The same USM may also be used on convection-cooled PMCs and XMCs or main M-Modules. A new design is then limited to the USM module and the FPGA content and therefore saves development time and costs. A Nios soft processor implemented in the Cyclone II FPGA by Altera provides local intelligence where needed.

The growing range of Wishbone-based standard IP cores from MEN comprise different UARTs, Ethernet, fieldbus interfaces, digital I/O etc. For users that like to write and/or implement specific IP cores on their own a complete development kit is available. The kit is based on a function-identical convection-cooled PMC module with front I/O.

The USM concept has been developed for harsh environment. Therefore, the P598 uses robust connectors to the USM, while all other components are soldered, and operates in a -40 to +85 °C temperature range with qualified components.

The P598 is a conduction-cooled PMC mezzanine card suitable for any compliant host carrier board in any type of bus system, i.e. CPCI, VME or on any type of stand-alone SBC. Appropriate carrier cards in 3U, 6U andother formats are available from MEN or other manufacturers.

Features

  • Main PMC for USM Universal Submodules
  • Conduction-cooled (CCPMC)
  • 1 USM slot
  • 1 FPGA 33,216 LE (for user-defined I/O and Nios soft core)
  • 32 MB DDR2 SDRAM
  • 2 MB Flash
  • -40 to +85°C with qualified components

Specifications

Functionality
  • User-defined through FPGA
  • Line drivers and/or additional hardware implemented on USM Universal Submodule (not included)
Memory
  • 32MB SDRAM memory
    • Soldered
    • DDR2
    • 132MHz memory bus frequency
    • FPGA-controlled
  • 2MB non-volatile Flash
    • For FPGA data and Nios firmware
    • FPGA-controlled
FPGA
USM Slot
  • One slot for a standard USM module
  • For implementation of line drivers and/or additional hardware
Miscellaneous
  • Eight onboard LEDs, FPGA-controlled
  • I²C interface to detect the USM module
PMC Characteristics (PCI)
  • Compliant with PCI Specification 2.2
  • 32-bit/33-MHz, 3.3V V(I/O)
  • Target
Peripheral Connections
Via Pn4 rear I/O connector
Electrical Specifications
  • Isolation voltage:
    • Voltage depends on implementation and signal routing of USM
  • Supply voltage/power consumption:
    • +5V (-3%/+5%), FPGA idle / US0 plugged: approx. 118mA, memory test / US0 plugged: 122mA
    • +3.3V (-5%/+5%), FPGA idle / US0 plugged: 76mA, memory test / US0 plugged: 82mA
  • MTBF: 848,597h @ 40°C according to IEC/TR 62380 (RDF 2000)
Mechanical Specifications
  • Dimensions: conforming to IEEE 1386.1
  • In accordance with VITA 20 (proposed Draft Standard for Conduction Cooled PMC)
  • Weight: 36g (w/o USM module)
Environmental Specifications
  • Temperature range (operation):
    • -40..+85°C, conduction-cooled
    • Airflow: min. 10m³/h
  • Temperature range (storage): -40..+85°C
  • Relative humidity (operation): max. 95% non-condensing
  • Relative humidity (storage): max. 95% non-condensing
  • Altitude: -300m to + 3,000m
  • Shock: 15g/11ms
  • Bump: 10g/16ms
  • Vibration (sinusoidal): 2g/10..150Hz
  • Conformal coating on request
Safety
PCB manufactured with a flammability rating of 94V-0 by UL recognized manufacturers
EMC
  • Radio disturbance: no connection outside housing, therefore radio disturbance not relevant
  • ESD/burst: no external interface connector, therefore ESD and burst not relevant
Software Support

Downloads