P511
Dual Fast Ethernet PMC

Main Features
- 2 full-duplex or half-duplex channels
- 10Base-T and 100Base-TX physical layer
- MAC layer realized in FPGA
- Local or external data buffer
- 6 additional GPIOs
- Fully integrated to comply with IEEE802.3
- 500 VAC isolation voltage
- -40 to +85°C with qualified components
- 32-bit/33-MHz PMC
- PMC based on USM concept
- Individual FPGA configuration
The P511 is a 32bit/33MHz PMC with dual Ethernet functionality. The two channels can be accessed via two RJ45 connectors which are led to the front via an adapter cable from a SCSI connector. They support half duplex and full duplex operation.
The PMC offers the possibility to buffer all receive and transmit Ethernet frames either in a local or in an external data buffer. This makes it possible to provide a Worst Case Execution Time analysis which makes it particularly well suited for safety-critical applications.
Up to 6 GPIO lines can be used on the module for additional functionality.
The P511 is based on the USM concept. USM Universal Submodules make PMC modules more flexible than ever. The Ethernet functionality is realized via an IP core implemented inside its onboard FPGA. This function can be changed at any time through implementation of different IP cores. The corresponding line drivers are realized on the USM which is simply plugged on the P511. One alternative function is the combination of an Ethernet core with a fieldbus interface to build gateways.
The I/O mezzanine module is suitable for any PMC compliant host carrier board in any type of bus system, i.e. CPCI, VME or on any type of stand-alone SBC in telecommunication, industrial, medical, transportation or aerospace applications. It offers long-term availability for at least 10 years and is qualified for operation in the extended temperature range.
- Two 10/100Base-T Ethernet channels
- Accessible on two RJ45 connectors via adapter cable
- Half duplex/full duplex support
- 32MB SDRAM memory
- Soldered
- DDR2
- 132MHz memory bus frequency
- FPGA-controlled
- 2MB non-volatile Flash
- For FPGA data and Nios firmware
- FPGA-controlled
- Standard factory FPGA configuration:
- Main bus interface
- Interrupt controller, SMBus controller
- 16Z087_ETH - Ethernet MAC IP core (2 IP cores for the 2 channels)
- 16Z043_SDRAM - SDRAM controller
- 16Z045_FLASH - Flash interface
- 16Z034_GPIO - GPIO controllers (2 IP cores, for onboard LEDs and 8-bit I/O)
- The FPGA offers the possibility to add customized I/O functionality. See FPGA.
- Compliant with PCI Specification 2.2
- 32-bit/33-MHz, 3.3V V(I/O)
- Target and initiator
- Via front panel on a shielded 50-pin HP D-Sub SCSI 2 receptacle connector
- Adapter cable to two RJ45 connectors included in the delivery
- Isolation voltage:
- 500 VAC
- Supply voltage/power consumption:
- +5V (-3%/+5%), 40mA
- +3.3V (-5%/+5%), 139mA
- Dimensions: conforming to IEEE 1386.1
- Weight: 78g
- Temperature range (operation):
- -40..+85°C
- Airflow: min. 1.0m/s
- Temperature range (storage): -40..+85°C
- Relative humidity (operation): max. 95% non-condensing
- Relative humidity (storage): max. 95% non-condensing
- Altitude: -300m to + 3,000m
- Shock: 15g/11ms
- Bump: 10g/16ms
- Vibration (sinusoidal): 1g/10..150Hz