The Nios-CompactPCI Open Platform FPGA Development Package can be used on the 3U CompactPCI slave card F206N. It includes a sample design with an internal PCI system unit, integrating the standard Wishbone and the Altera Avalon bus.
The PCI system unit forms the interface to the PCI bus, where the F206N can then be addressed as a PCI slave. It connects to the Wishbone bus where an SDRAM and a Flash controller are already implemented. The user can now add any kind and number of IP cores to the Wishbone bus by using MEN's Wishbone Bus Maker tool, which is part of the package and which can be used to generate the Wishbone bus. The Wishbone Bus Maker can generate multi-master and multi-slave bus systems.
A Wishbone-to-Avalon-bridge and vice versa, an Avalon-to-Wishbone-bridge - both developed by MEN - allow the additional integration of Avalon-based IP cores and especially of the Nios soft core from Altera. Nios connects to the Avalon bus, where a GPIO module for user LED control is already implemented as well. The user can now also add any kind and number of IP cores to the Avalon bus by using the SOPC Builder tool from Altera. The SOPC builder is a part of the Quartus II development package of Altera - see www.altera.com. It is not part of MEN's Nios-CompactPCI Open Platform FPGA Development Package.
Nios-CompactPCI Open Platform FPGA Development Package (MEN) (without Altera Quartus II) (license not included in F206N)