The CS1 is a FPGA chip with an AFDX-protocol that can be installed directly onto a large variety of boards to build an AFDX end system, and eliminates the need for an additional module. Without modification, the CS1 can be adapted to realize specific requirements like, for example, AFDX/CAN, AFDX/Standard Ethernet, AFDX/ARINC 429 gateway solutions.
AFDX is a reliable, high-speed data bus commonly used in airborne applications for sending information between avionics subsystems. In modern aircraft avionic architectures, AFDX it is used to connect an arbitrary unit or module with other aircraft equipment, executing a full featured ARINC-653 application interface, which is equipped with a proprietary runtime executive. Its most important features are high data integrity, redundancy and deterministic behavior.
The CS1 meets all AFDX safety and performance requirements, which makes it ideal for safety-critical inflight data transfer. It also supports two full duplex AFDX networks based on standard IEEE802.3 Ethernet technology and applies protocol stack implementation. Up to 256 fully separated receive VLs and 64 transmit VLs allow for reliable packet transport and bounded transport latency.
The CS1, which can be ordered as an individual chip, is also available on the P522, a PMC I/O mezzanine card which is suitable for any PMC compliant host carrier board.
- AFDX functionality integrated in a Flash based FPGA
- SEU immune configuration
- On-board AFDX protocol stack implementation
- Interoperable with Airbus and Boeing
- DAL-D certifiable/prepared for DAL-A
- Host driver with ARINC-653 compliant port API
- Integrated SNMP/ICMP agent
- Implemented on the P522 AFDX Interface PMC
- AFDX Usage Domain
- Compatible with Airbus End System Detailed Functional Specification
- Receive Operation
- Up to 256 virtual reception links (VL)
- Up to 32 ports per VL
- Up to 1024 receive ports in total
- Transmit Operation
- Up to 64 virtual transmission links (VL)
- Up to 32 ports per VL
- Up to 1024 transmit ports in total
- BAG between 0.1 ms and 204.7 ms in steps of 0.1 ms
- Support of AFDX Queueing and Sampling Ports as defined in ARINC664-P7
- Support of SAP and extended SAP as defined in ARINC664-P7
- Support of direct communication via IP layer
- Support of Management Information Base (MIB) for AFDX and SAP communication as defined in ARINC664-P7
- Reserved Bridge I/O Domain
- Prepared for additional bus interfaces accessible by the host (on request)
- AUX Domain
- SNMP Agent
- ICMP Agent
- Completely independent of host communication
- Memory Size Support
- AFDX TX/RX buffer support:
- Up to 32 MB receive data
- Up to 32 MB transmit data
- FPGA-controlled and ECC/CRC protected
- Up to 128 MBit non-volatile Flash
- For AFDX configuration data
- FPGA-controlled and CRC protected
- Minimum support of 16 AFDX configurations in Flash
- External Interfaces
- 6 General Purpose Digital Inputs usable for:
- Location indication
- In flight / on ground indication
- PCI slave
- MII AFDX Channel A/B
- SPI Flash Memory
- Store AFDX configuration tables
- 2x RAM Buffer Memory
- UART AUX COM
- Independent debug and test interface for the AUX domain
- JTAG
- Access to FPGA for programming, debugging and testing
- Configuration Interfaces
- Software tool for programming AFDX configuration
- ARM Cortex-M3 (SNMP/ICMP) enable
- AFDX configuration write protection enable
- FPGA
- Complete AFDX protocol implementation
- SEU immune configuration
- SNMP and ICMP agents
- Electrical Specifications
- Supply voltage
- 1.2 V Core Supply
- 2.5 V IO Supply for SRAM Interface
- 3.3 V IO Supply for PCI Interface
- Power consumption
- Environmental Specifications (Dependent on Host Board)
- Temperature range (operation):
- Temperature range (storage): -55 to +150°C
- Reliability
- MTBF
- Software Support
- Short-form Data Sheet
- User Manuals
- Technical Drawings
- Errata & Technical Information
- Presentations
- Quality & Legal
